1. Field of the Invention
This invention relates generally to the field of microprocessors and, more particularly, to execution units within microprocessors.
2. Description of the Related Art
Microprocessors are typically designed to include a limited number of architectural registers. Architectural registers are often used by instructions to store intermediate and final results prior to storing the results to a cache or a main memory. Instructions often write results to at least one destination register. Consequently, the limited number of architectural registers, can limit the number of instructions that can be in flight in a microprocessor since most instructions will require at least one physical register for a destination register. The number of architectural registers can further limit the number of instructions in flight when register dependencies arise. Dependencies can arise when two or more instructions attempt to access or update the same register.
A register renaming scheme can be implemented to more efficiently use a limited number of architectural registers. A register renaming scheme can allow more instructions to be in flight in a microprocessor and can reduce latencies from register dependencies. Generally speaking, register renaming schemes work by assigning one or more physical registers in place of architectural registers and tracking these register assignments. An architectural register list can be used to track the register assignments to determine which physical register or registers contain the contents of a particular architectural register at any given time. Processors may include more physical registers than architectural registers. The physical registers can be continually reused when they no longer comprise part of the current state, also referred to as the architectural state, of the microprocessor. Physical registers that do not comprise part of the architectural state can comprise part of the speculative state. Generally speaking, the speculative state of a physical register can be committed to the architectural state when the instruction corresponding to the physical register is retired.
Microprocessors will often be required to abort instructions that comprise the speculative state. When an abort is received, the physical registers that comprise the speculative state must be restored to a non-speculative state to allow the microprocessor to continue to execute instructions following the abort. Restoring physical registers to a non-speculative state can be a difficult and complex process. The process can consume a large number of execution latencies. An apparatus and method for reducing the latency following an abort is needed.
The problems outlined above are in large part solved by an apparatus and method as described herein. Generally speaking, an apparatus and method for implementing a register free list scheme is provided. An instruction received in an execution unit can be assigned an absolute register number as its destination register. A new physical register tag from a free list can be assigned to the absolute register number, and a tag future file can be updated with the new physical register tag. The old physical register tag can be read from the tag future file and stored in a retire queue entry corresponding to the instruction along with the new physical register tag and an architectural register identifier corresponding to the absolute register number. A valid bit corresponding to the entry can be set in response to the entry being written. In response to an abort signal, a swap bit corresponding to the entry can be set, the valid bit can be reset, and the new physical register tag can be conveyed to a rename unit in response to receiving a free register request. In response to the entry being retired prior to receiving an abort signal, the valid bit corresponding to the entry can be reset and the old physical register tag can be conveyed to a rename unit in response to receiving a free register request.
Broadly speaking, a retire queue is contemplated. The retire queue includes a plurality of entries. The plurality of entries include a swap bit, a valid bit, an architectural register identifier, a first register tag, and a second register tag. The retire queue also includes a free list. The free list includes the first register tag of each of the plurality of entries whose swap bit corresponds to a first value. The free list also includes the second register tag for each of the plurality of entries whose swap bit corresponds to a second value and whose valid bit corresponds to the first value.